Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.
Flash memory devices have undergone rapid development. Flash memory devices can store data for a considerably long time without powering (i.e., they are a form of non-volatile memory), and have advantages such as high integration level, fast access, easy erasing, and rewriting. To further improve the bit density and reduce cost of flash memory devices, three-dimensional NAND flash memory devices have been developed.
A three-dimensional NAND flash memory device includes a stack of gate electrodes arranged over a substrate, with a plurality of semiconductor channels through and intersecting word lines, into the p- and/or n-type implanted substrate. The bottom/lower gate electrodes function as bottom/lower selective gates (BSG). The top/upper gate electrodes function as top/upper selective gates (TSG). Back-End-of Line (BEOL) Metal plays the role of Bit-Lines (BLs). The word lines/gate electrodes between the top/upper selective gate electrodes and the bottom/lower gate electrodes function as word lines (WLs). The intersection of a word line and a semiconductor channel forms a memory cell. WLs and BLs are typically laid perpendicular to each other (e.g., in an X-direction and a Y-direction), and TSGs are laid in a direction perpendicular to both the WLs and BLs (e.g., in a Z-direction.)
Chemical etching of semiconductor wafers using wet etchants is commonly performed in the industry to remove various materials, or to etch the semiconductor wafer itself. The wafers to be subjected to the chemical etch are placed in a solution bath containing a particular chemical etchant for a period of time that determines how much material is etched away. It can be challenging to control the etch rate for a given material layer on the wafers after the wafers have been placed into the chemical bath.